Tile Vertex Instruction Set Architecture for Mk2 IPUs with FP8 Support

The tile vertex instruction set architecture (ISA) document describes the subset of the IPU instruction set used by the Worker threads on the Mk2 IPUs with FP8 support.

Tile vertex ISA for the Mk2 IPU with FP8 support (pdf)

  • There may be links in the document to unreleased information.

  • In the document, IPU21 is a codename for the Mk2 IPU with FP8 support, as used in the C600 PCIe IPU card.

For information on programming in assembly see the Poplar and PopLibs User Guide which describes the vector types and how to write vertices in assembly.