Tile Vertex Instruction Set Architecture for Mk2 IPUs

The tile vertex instruction set architecture (ISA) document describes the subset of the IPU instruction set used by the Worker threads on the Mk2 IPUs.

Tile vertex ISA for the Mk2 (GC200 and Bow) IPU (pdf)

  • There may be links in the document to unreleased information.

  • In the document, IPU2 is a codename for the Mk2 architecture used in the IPU-M2000 and Bow-2000 IPU-Machines.

For information on programming in assembly see the Poplar and PopLibs User Guide which describes the vector types and how to write vertices in assembly.